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SY89467U precision lvpecl 1:20 fanout with 2:1 mux and internal termination with fail-safe input precision edge is a registered trademark of micrel, inc. micro leadframe and mlf are registered trademarks of amkor technology, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 general description the SY89467U is a 2.5/3.3v, 1:20 lvpecl fanout buffer with a 2:1 differential input multiplexer (mux). a unique fail-safe input (fsi) protection prevents metastable output conditions when the selected input clock fails to a dc voltage (when voltage between the pins of the differential input drops significantly below 100mv). the differential input includes micrel?s unique, 3-pin internal termination architecture that can interface to any differential signal (ac- or dc-coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor networks in the signal path. the outputs are 800mv, lvpecl with fast rise/fall times guaranteed to be less than 270ps. the SY89467U operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full industrial temperature range of ?40c to +85c. the SY89467U is part of micrel?s high-speed, precision edge ? product line. all support documentation can be found on micrel?s web site at: www.micrel.com . functional block diagram precision edge ? features ? selects between two inputs, and provides 20 precision lvpecl copies ? fail-safe input ? prevents outputs from oscillating when input is invalid ? guaranteed ac performance over temperature and supply voltage: ? dc-to >1.5 ghz throughput ? < 1200ps propagation delay (in-to-q) ? 270ps rise/fall times ? ultra-low jitter design: ? <1ps rms random jitter ? <1ps rms cycle-to-cycle jitter ? <10ps pp total jitter (clock) ? <0.7ps rms mux crosstalk induced jitter ? unique, patented mux input isolation design minimizes adjacent channel crosstalk ? unique patented internal termination and vt pin accepts dc- and ac-coupled inputs (cml, pecl, lvds) ? wide input voltage range: v cc to gnd ? 2.5v 5% or 3.3v 10% supply voltage ? -40c to +85c industrial temperature range ? available in 64-pin tqfp package applications ? fail-safe clock protection ? sonet clock distribution ? backplane distribution markets ? lan/wan ? enterprise servers ? ate ? test and measurement
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 2 ordering information (1) part number package type operating range package marking lead finish SY89467Uhy t64-1 industrial SY89467Uhy with pb-free bar-line indicator matte-sn pb-free SY89467Uhytr (2) t64-1 industrial SY89467Uhy with pb-free bar-line indicator matte-sn pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 64-pin epad-tqfp (t64-1)
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 3 pin description pin number pin name pin function 1, 16, 23, 33 41, 48, 58 vcc positive power supply: bypass with 0.1f||0.01f low esr capacitors as close to the v cc pins as possible. 64, 63 62, 61 60, 59 57, 56 55, 54 53, 52 51, 50 47, 46 45, 44 43, 42 39, 38 37, 36 35, 34 31, 30 29, 28 27, 26 25, 24 22, 21 20, 19 18, 17 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 q6, /q6 q7, /q7 q8, /q8 q9, /q9 q10, /q10 q11, /q11 q12, /q12 q13, /q13 q14, /q14 q15, /q15 q16, /q16 q17, /q17 q18, /q18 q19, /q19 lvpecl differential output pairs: differential buffered output copies of the selected input signal. the output swing is typically 800mv. u nused output pairs may be left floating with no impact on jitter. see ?lvpecl output terminati on? subsection. normally terminated with 50 ? to v cc -2v. these differential lvpecl outputs are a logic function of the in0, in1, and sel inputs. see ?truth table? below. 4, 13 vref-ac0 vref-ac1 reference voltage: these outputs bias to v cc ?1.2v. they are used for ac-coupling inputs in and /in. connect vref-ac directly to the corresponding vt pin. bypass with 0.01f low esr capacitor to v cc . due to limited drive capability, each vref-ac pin is only intended to drive its respective vt pin. maximum sink/s ource current is 0.5ma. see ?input interface applications? subsection. 5, 12 vt0, vt1 input termination center-tap: each side of a diffe rential input pair terminates to the vt pin. the vt pin provides a center-tap for each in put (in, /in) to a termination network for maximum interface flexibility. see ?input interface applications? subsection. 6, 7 10, 11 in0, /in0 in1, /in1 differential inputs: these input pairs are the di fferential signal inputs to the device. these inputs accept ac- or dc-coupled signals as sm all as 100mv. the input pairs internally terminate to a vt pin through 50 ? . this allows a wide input voltage range from vcc to gnd. see figure 3a, simplified differential input stage for details. note that when these inputs are left in an open state, the fsi feature will override this input state and provide a valid state at the output. see ?functi onal description? subsection. 2, 3, 14, 15, 32, 40, 49 gnd, exposed pad ground. exposed pad must be connected to a groun d plane that is the same potential as the ground pins. 9 oe single-ended input: this ttl/cmos input dis ables and enables the q0-q19 outputs. it is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. when disabled, q goes low and /q goes high. oe being synchronous, outputs will be enabled/disabled following a rising and a falling edge of the input clock. v th = v cc /2. 8 sel single-ended input: this single-ended ttl/cmos-c ompatible input selects the inputs to the multiplexer. note that this inpu t is internally connected to a 25k ? pull-up resistor and will default to logic high state if left open. v th = v cc /2. truth table inputs outputs in0 /in0 in1 /in1 sel q /q 0 1 x x 0 0 1 1 0 x x 0 1 0 x x 0 1 1 0 1 x x 1 0 1 1 0
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 4 absolute maximum ratings (1) supply voltage (v cc ) ..........................?0.5v to +4.0v input voltage (v in ) ..................................?0.5v to v cc lvpecl output current (i out ).................................... continuous ................................................. 50ma surge........................................................ 100ma current (v t ) source or sink on vt pin........................ 100ma input current source or sink current on (in, /in) ........... 50ma current (v ref ) source/sink current on v ref-ac (4) ........... 0.5ma maximum operating junc tion temperature .....125c lead temperature (soldering, 20 sec.) ..........+260c storage temperature (t s )..................?65c to 150c operating ratings (2) supply voltage (v cc ).................. +2.375v to +2.625v ......................................................+3.0v to +3.6v ambient temperature (t a )?????-40c to +85c package thermal resistance (3) tqfp ( ja ) still-air ..................................................... 35c/w tqfp ( jb ) junction-to- board .................................... 21c/w dc electrical characteristics (5) t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 3.0 2.5 3.3 2.625 3.6 v v i cc power supply current no load, max v cc 120 165 ma r in input resistance (in-to-v t ) 45 50 55 ? r diff_in differential input resistance (in-to-/in) 90 100 110 ? v ih input high voltage (in, /in) 0.1 v cc v v il input low voltage (in, /in) 0 v ih ?0.1 v v in input voltage swing (in, /in) see figure 2a. note 6. 0.1 1.0 v v diff_in differential input voltage swing |in-/in| see figure 2b. 0.2 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v ref-ac output reference voltage i vref-ac = + 0.5ma v cc ?1.3 v cc ?1.2 v cc ?1.1 v v t_in voltage from input to v t 1.28 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than thos e detailed in the operational sections of this data sheet. exposure to absolute maximu m rating conditions for extended periods ma y affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the p cb. ja and jb values are determined for a 4-layer board in still air unless otherwise stated. 4. due to limited drive capability use for input of the same package only. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 6. v in (max) is specified when v t is floating.
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 5 lvpecl outputs dc electrical characteristics (7) v cc = 2.5v 5% or 3.3v 10%; r l = 50 ? to v cc -2v; t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage q, /q v cc -1.145 v cc -0.895 v v ol output low voltage q, /q v cc -1.945 v cc -1.695 v out output voltage swing see figure 2a. 550 800 950 mv v diff_out differential output voltage swi ng see figure 2b. 1100 1600 1900 mv lvttl/cmos dc electri cal characteristics (7) v cc = 2.5v 5% or 3.3v 10%;t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a note: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 6 ac electrical characteristics ( 8 ) v cc = 2.5v 5% or 3.3v 10%; r l = 50 ? to v cc -2v; input t r /t f < 300ps; t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v out 200mv, v in 200mv 1.5 2.0 ghz f max maximum operating frequency v out 200mv, v in 100mv 1.0 1.5 ghz differential propagation delay in-to-q 100mv < v in 200mv, note 9 600 850 1200 ps in-to-q 200mv < v in 800mv, note 9 500 750 1100 ps t pd sel-to-q v th = v cc /2 350 600 850 ps t s oe set-up time oe-to-in note 10 300 ps t h oe hold time in-to-oe note 10 800 ps output-to-output skew note 11 15 35 ps input-to-input skew note 12 5 20 ps t skew part-to-part skew note 13 300 ps clock random jitter note 14 1 ps rms cycle-to-cycle jitter note 15 1 ps rms total jitter note 16 10 ps pp t jitter crosstalk-induced jitter note 17 0.7 ps rms t r, t f output rise/fall time (20% to 80% ) at full output swing. 110 170 250 ps v in > 200mv 45 55 % duty cycle 100mv < v in 200mv 45 55 % notes: 8. high-frequency ac-parameters are guaranteed by design and characterization. 9. propagation delay is measured with input t r , t f 300ps (20% to 80%). the propagation delay is a function of the rise and fall times at in. see ?typical operating char acteristics? for details. 10. set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. for asyn chronous applications, set-up and hold do not apply. 11. output-to-output skew is measured between tw o different outputs under identical transitions. 12. input-to-input skew is the time difference between the two inputs to one output, under identical input transitions. 13. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs. 14. random jitter is measured with a k 28.7 character pattern, measured at micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 7 functional description clock select (sel) sel is an asynchronous ttl/cmos compatible input that selects one of the two input signals. an internal 25k ? pull-up resistor defaults the input to logic high if left open. input switching threshold is v cc /2. refer to figure 1a. fail-safe input (fsi) the input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mv pk , typically 30mv pk . maximum frequency of the SY89467U is limited by the fsi function. refer to figure 1b. input clock failure case if the input clock fails to a fl oating, static, or extremely low signal swing such that the voltage across the input pair is significantly less than 100mv, fsi function will eliminate a metastable condition and latch the outputs to the last valid state. no ringing and no undetermined state will occur at the out put under these conditions. the output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30mv. note that the fsi function will not prevent duty cycle distortion in case of a sl owly deteriorating (but still toggling) input signal. due to the fsi function, the propagation delay will depend on the rise and fall time of the input signal and on its amplitude. output enable (oe) oe is a synchronous ttl/cmos compatible input that enables/disables the outputs based upon the input to this pin. the enable function is synchronous so that the clock outputs will be enabled or disabled following a rising and a falling edge of the input clock. refer to figure 1c. internal 25k ? pull-up resistor defaults the input to logic high if left open. input switching threshold is v cc /2.
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 8 timing diagrams figure 1a. sel-to-q delay figure 1b. fail-safe feature
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 9 figure 1c. enable output timing diagram figure 1d. propagation delay figure 1e. setup and hold time
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 10 typical operating characteristics v cc = 3.3v, gnd = 0v, v in = 200mv, r l = 50 ? to v cc ?2v; t a = 25c, unless otherwise stated.
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 11 functional characteristics v cc = 3.3v, gnd = 0v, v in = 100mv, r l = 50 ? to v cc -2v; t a = 25c, unless otherwise stated.
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 12 single-ended and di fferential swings figure 2a. single-ended voltage swing figure 2b. differential voltage swing input and output stages figure 3a. simplified differential input stage figure 3b. simplified differential output stage
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 13 input interface applications figure 4a. lvpecl interface (dc-coupled) figure 4b. lvpecl interface (ac-coupled) option: may connect v t to v cc figure 4c. cml interface (dc-coupled) figure 4d. cml interface (ac-coupled) figure 4e. lvds interface (dc-coupled)
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 14 pecl output interface applications pecl has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low emi. pecl is ideal for driving 50ohm and 100ohm-controlled impedance transmission lines. there are several techniques for terminating the pecl output: parallel termination- thevenin equivalent, parallel termination (3-resistor), and ac-coupled termination. unused output pairs may be left floating. however, single-ended outputs must be terminated or balanced. figure 5a. parallel termination-thevenin equivalent figure 5b. parallel termination (3-resistor) related product and su pport documentation part number function data sheet link sy89468u precision lvds 1:20 fanout mux with 2:1 mux and internal termina tion with fa il safe input http://www.micrel.com/_pdf/hbw/SY89467U.pdf#page=2 mlf ? application note www.amkor.com/products/not es_papers/mlfappnote.pdf hbw solutions new products and applications www.micrel.com/product-info/products/solutions.shtml
micrel, inc. SY89467U april 2008 m9999-040808-c hbwhelp@micrel.com or (408) 955-1690 15 package information 64-pin epad-tqfp (t64-1) packages notes: 1. package meets level 2 moisture sensitivity classification. 2. all parts are dry-packed before shipment. 3. exposed pad must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authoriz ed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended fo r surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support appliances, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2007 micrel, inc.

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